10. CACHE Instructions

10.6 Index Load Tag (D)

Index Load Tag (D) reads the primary data cache tag fields into the CP0 TagLo and TagHi registers. VA[13:5] defines the address and VA[0] defines the way of the tag to be read.

All parity errors caused by Index Load Tag (D) are ignored. The following mapping defines the operation:

TagLo[0] = Tag parity bit

TagLo[1] = SCWay

TagLo[2] = State parity bit

TagLo[3] = LRU bit

TagLo[7:6] = State bits

TagLo[31:8] = Tag[35:12]

TagHi[3:0] = Tag[39:36]

TagHi[31:29] = StateMod bits

All other CP0 TagLo and TagHi bits are set to 0.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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